1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of semiconductor devices, and, more specifically, to various methods of modulating strain in PFET and NFET FinFET semiconductor devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
FIG. 1 is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed in a semiconductor substrate 12. The device 10 includes three illustrative fins 14, a gate structure 16, sidewall spacers 18 and a gate cap layer 20. The gate structure 16 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material, and one or more conductive material layers (not separately shown) that serve as the gate electrode for the device 10. In this example, the fins 14 are comprised of a substrate fin portion 14A and an alternative fin material portion 14B. The substrate fin portion 14A may be made of silicon, i.e., the same material as the substrate, and the alternative fin material portion 14B may be made of a material other than the substrate material, for example, silicon-germanium. The fins 14 are typically formed by etching a plurality of trenches 13 into the substrate 12. A recessed layer of insulating material (not shown) is normally positioned in the trenches 13 between the fins 14. The fins 14 have a three dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device 10 when it is operational. The portions of the fins 14 covered by the gate structure 16 are the channel regions of the FinFET device 10. In a conventional process flow, the portions of the fins 14 that are positioned outside of the spacers 18 correspond to the source/drain regions of the device 10.
Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower production costs relative to previous device generations. Thus, device designers spend a great amount of time and effort to maximize device performance while seeking ways to reduce manufacturing costs and improve manufacturing reliability. Device designers are currently investigating using alternative semiconductor materials, such as so-called SiGe, Ge and III-V materials, to manufacture FinFET devices which are intended to enhance the performance capabilities of such devices at a given supply voltage or to enable lower-voltage operation without degrading their operating speed. For P-type FinFET devices having a germanium-containing channel material, such as substantially pure germanium, the performance of such devices is increased if the channel material is compressively strained, while the performance of such P-type FinFET devices degrades if the channel material is under a tensile strain. Conversely, N-type FinFET devices can exhibit increased performance when formed using substantially unstrained SiGe or tensile strained material for the channel region. The problem is that, in traditional manufacturing techniques, fins for all of the devices (both N and P) are formed at the same time across the substrate so as to enable precise formation of the fins without concern for dimensional variations in the fins due to so-called etch loading effects. Thus, using prior art manufacturing techniques, the formation of, for example, germanium-containing fins with acceptable strain conditions for both N and P type devices is problematic.
The present disclosure is directed to various methods that may solve or reduce one or more of the problems identified above.